This invention relates to a digital integrated circuit and, more particularly, to a integrated logic circuit capable of simplifying a test.
Serial scan and random scan are both conventional well-known methods used for simplifying a test of integrated logic circuits. Using these methods, the process of reading out data from a memory element of the logic integrated circuit in a test mode is different between these methods, depending on the serial access or random access, but there is a common feature that data is read out at the same time.
However, in the case where the contents of a register (memory element) are traced in a certain period, using the methods described above, it is necessary to read out the result of tracing for each clock or instruction while the test mode and an execution mode are performed repeatedly. This necessitates complicated control operation and a long test time for the logic integrated circuit. Thus, the logic integrated circuit and test program for the logic integrated circuit using the methods described above have to be further improved.